Low voltage CMOS amplifier

ABSTRACT

A low voltage CMOS amplifier, particularly adaptable for use with an oscillator in an electronic watch. The relatively large biasing resistor used in prior art CMOS amplifiers is eliminated and transistors are provided in a network to provide proper biasing and also enable the amplifier to operate at a lower power supply voltage than prior art amplifiers.

United States Patent Hoffmann l June 3, 1975 [54] LOW VOLTAGE CMOSAMPLIFIER 3.676.80l 7/1972 Musa 33l/116 3 7 i [75] Inventor. KurtHoffmann, Sunnyvale Calif. 9/1973 33mm [73] Assignee: American Micro-Systems, lnc., P i E miner john Kominski Sam?! Clam Callf- Attorney.Agent, or FirmOwen, Wickersham & 1221 Filed: Jan. 24, 1974 Emkso" 4 i 1pp NO 36 151 [57] ABSTRACT 52 us. (:1 A. 330/35; 330/13; 331/116 R A l Qamplifier adaptable [5 l] m C] H03! 3/16 for use with an osc1llator manelectronic watch. The [58} Fie'ld l 8 35 relatively large biasingresistor used in prior art CMOS i i 33U] amplifiers is eliminated andtransistors are provided in a network to provide proper biasing and alsoenable [56] References Cited the amplifier to operate at a lower powersupply volt- UNITED STATES PATENTS age than prior art amplifiers.

3.664,] 111 5/1972 Walton 331/116 5 Claims 6 Drawing Figures Q cc BP 6Ol I} 48 I (T F2 l I 50 t/30111,)

40 3a 36 k L -v 45 44 58 1L 1 fi "32 (Tm) BN (T (I 2) LOW VOLTAGE CMOSAMPLIFIER BACKGROUND OF THE INVENTION This invention relates to anelectronic amplifier particularly adapted for implementation incomplementary conductor devices such as npn and pup transistors or CMOSdevices.

Complementary MOS devices utilizing both P- channel and N-channeltransistors have been used extensively in products such as watchesbecause of their inherent low power characteristics. However, theconventional CMOS amplifier heretofore devised could only be DC-biasedif its power supply voltage was larger than the sum of the thresholdvoltages of its two complementary transistors. In situations where thepower supply voltage available was limited, this imposed a seriousprocessing limitation. Also, the prior CMOS amplifier circuit required arelatively large biasing resistor in order to avoid unnecessaryattenuations. When using a standard MOS process, it was almostimpossible to implement such a high resistance with reasonableprecision.

It is therefore one object of the present invention to provide animproved CMOS circuit that solves the aforesaid problems.

Another object of the present invention is to provide a CMOS amplifierwhich will operate satisfactorily when the power supply voltage is onlyenough to ex ceed the separate threshold voltage of each complementarytransistor.

Another object of the present invention is to provide a CMOS amplifierthat eliminates the need for a biasing resistor thereby making itpossible to use conventional MOS process techniques that are economicaland have high yield factors.

Yet another object of the present invention is to provide a CMOSamplifier that is particularly adaptable for use in electronic watchesand that can be readily combined with conventional components such ascapacitors and crystal vibrators to provide an oscillator circuit.

SUMMARY OF THE INVENTION The aforesaid and other objects of theinvention are accomplished by a CMOS amplifier circuit wherein thebiasing of the two complementary amplifying transistors connectedbetween the regular power source and ground, as required to provideamplification in the well known push-pull type arrangement, isaccomplished by a separate network of biasing transistors for eachamplifying transistor. Each such network is in effect a dividercomprised of two transistors connected together between the power sourceand ground with the output of the divider being applied as the biasingvoltage to the gate of the amplifying transistor. The need for the longfeedback resistor used in prior art CMOS amplifying circuits iseliminated. More importantly, the voltage required to operate theamplifier need only be greater than the threshold voltage of eachamplifying transistor instead of greater than the combined thresholdvoltages of both amplifying transistors, as in the prior art. Theamplifying circuit may be readily combined with conventional oscillatorssuch as the Pierce type and is particularly adaptable for use in small,low power consuming devices such as watches.

Other objects, advantages and features of the present invention willbecome apparent from the following detailed description which ispresented in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a circuit diagram of a CMOSamplifier of the prior art;

FIG. 2 is a circuit diagram of a CMOS amplifier embodying the principlesof the present invention;

FIG. 3 is a circuit diagram showing a modified form of the amplifier ofFIG. 2;

FIG. 4 is a diagram showing a standard form of crystal oscillator;

FIG. 5 is a circuit diagram showing the oscillator of FIG. 4 combinedwith an amplifier according to the present invention; and

FIG. 6 is a circuit diagram showing another oscillator-amplifier circuitembodying the principles of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS With reference to the drawing, FIG.1 shows a pushpull type amplifier circuit 10 of the prior art which isimplemented as a complementary metal-oxide-silicon (MOS) circuit whereina P-channel transistor I2 (T is connected from a supply voltage line Vto an N- channel transistor 14 (T connected to a ground line 16. From ajunction 18 between these transistors extends an output V,,. In orderfor such an amplifier to function properly, stable D.C. conditions mustbe established. Therefore, junction 18 is also connected through abiasing feedback resistor 20 to another junction 22 which is connectedby separate leads to the gates of both transistors 12 and 14. The inputVi'nto the amplifier is provided through a capacitor 24 to the junction22. In this circuit, the DC. biasing of the transistors is provided bythe voltage division at junction 22 which is fed back from the junction18 through the resistor 20 to both transistor gates. The capacitor 24prevents any reverse D.C. flow, so the DC. biasing provided isindependent of the Vin conditions. Now, when a sinusoidal or pulsinginput voltage (Vin) is applied, it passes through the relatively lowimpedance capacitor 24 and then, because of the relatively highimpedance resistor 20 is applied on the gates of both transistors l2 and14. This voltage change causes a large current flow through eachtransistor which amounts to a voltage increase or swing that is muchlarger than the input voltage Vin.

With the aforesaid prior art amplifier 10, it will be shown, as follows,that, for normal operation the supply voltage Vcc must be greater thanthe combined threshold voltages V and V of the two transistors.

In this derivation, both threshold voltages V and V are assumed to bepositive and it may also be assumed that the conduction factors for thetwo transistors are the same, so that K K,,.

Under DC conditions:

in a and (VI(' 0) V(( in)- Because both devices are in saturation:

IN: KN (V0 I/ and I, k, [V(( V0) V)? and IN The DC output voltage of theamplifier is:

(V0 VT") r'r' n tp) V0 1/2 (VCI rp in) I I The requirements for properDC-bias of the amplifier are:

and

li er T ml 0 where (V V,,,) is the overdrive of transistor T, and [V VV,,,] of transistor T Substituting equation i into equation 2, gives:

[ M rr' tp V02) m] O and thus:

V('( rn rp) This means that the amplifier can only be DC-biasedproperly, if the power supply voltage V is larger than the sum of thethreshold voltages.

Now, turning to FIG. 2, my improved amplifier a is shown which embodiesthe principles of the present invention and requires less power. Here,two complementary P-channel and N-channel MOS transistors (T and 32(TNl) are similarly connected together between the power line V and aground line 34, with a junction 36 between them providing the circuitoutput V The gate of the P-channel transistor 30 is connected by a lead38 through a capacitor 40 to a junction 42 and the gate of the N-channeltransistor is connected by a lead 44 through a similar capacitor 46 tothe same junction which is connected to the input to be amplified (Vin).Now, a first P-channel biasing transistor 48 (T is connected at itssource to the V Its gate and drain are connected together and to ajunction 50 in the lead 38 between the capacitor 40 and the gate oftransistor 30. Junction 50 is also connected to the drain of anotherN-channel transistor 52 whose source is connected to the ground line 34.The gate of this latter transistor is connected by a lead 54 to V Asimilar pair of biasing transistors are provided for the transistor 32.Thus, an N-channel transistor 56 is connected from its source to theground line while its gate and drain are connected together and to ajunction 58 in the lead 44 between the capacitor 46 and the gate oftransistor 32. The junction 58 is also connected to the drain of aP-channel transistor 60 whose source is connected to V and whose gate isconnected by a lead 62 to the ground line. Essentially, the transistors48 and 52 and the transistors 60 and 56 are all high impedance deviceswhich function as two separate divider networks that furnish the properD.C. biasing for the transistors 30 and 32 respectively. To achieveproper biasing of transistor 32 for example, the transistors 60 and 56are made of a size such that the transistor 60 functions basically as acurrent generator into the transistor 56 which provides a voltage dropat the junction 58 and thus at the gate of transistor 32. This drop islarger than the threshold voltage V of transistor 32. The biasingtransistor 52 works with transistor 48 in a similar way, transistor 52being essentially a current generator which creates a voltage dropacross transistor 48, thereby biasing transistor 30.

where (V V,,,) is the overdrive of transistor 32. The current throughthe biasing transistors T and T is respectively:

[1W3 nva i HN m) and 1w 'rm ni l with Substituting equation 6 into 5which is the requirement for proper biasing of transistor T Therequirement for biasing of transistor T is:

where V V,,,) is the overdrive of transitor T,, The current through Tand T is respectively:

ITNZ rwe zt' tn) and [TF2 rpa (VHF iv with substituting equation 9 into8:

V (ill) which is the requirement for proper biasing of transis tor TComparing the results from amplifier FIG. 1 V,-, V V 4 with the resultsfrom amplifier, FIG. 2

It is apparent that the voltage requirement for my amplifier circuit hasbeen considerably reduced.

The operation of the entire circuit may be described as follows: With aconstant voltage supplied between V and ground, assume that an input(Vin) of some predetermined frequency is applied to the input junction42. Since the resistivity of the capacitors 40 and 46 is low,essentially the same input appears in leads 38 and 44. Also, it may beassumed that the resistivity of all the biasing transistors 48, 60, 52and 56 is so high that they do not appreciably attenuate the inputsignal Vin. Now, as previously described, both of the transistors 30 and32 are being properly biased at this time through their respectivebiasing transistors. Therefore, with the Vin signal and the biasingvoltage applied to the gates of 30 and 32, output (V,,) of the circuitat the junction 36 is amplified in accordance with a built-in gainfactor that is dependent on the relative characteristics of the variousbiasing transistors.

Since it is desirable that the amplifier have a high input impedance,the transistors 30 and 32 for the amplifier a of FIG, 2 must berelatively long. As shown in the embodiment of FIG. 3, this disadvantagecan be avoided by connecting the gate of transistor 52 to lead 44 by alead 54a. Because this transistor 52 receiving only the bias voltageinstead of V on its gate, it has less overdrive than it has in thecircuit of FIG. 2. Thus, the actual length of this element can bereduced substantially. If desired, the same result can be accomplishedby connecting the gate of transistor 60 to lead 38.

As stated previously, the amplifier circuit 100 cmbodying the principlesof my invention is readily adaptable for use with an oscillator as a lowpower component of an electrical watch. A typical oscillator 62, knownas a Pierce oscillator, is shown diagrammatically in FIG. 4. Thisoscillator can be readily implemented in monolithic form with an M08transistor 64 as an active element, two external resistors 66 and 68,two capacitors 70 and 72 and a piezoelectric crystal vibrator 74. Thecircuit is connected between a suitable power source V and ground toexcite the crystal electrically and produce an oscillating output.Because this oscillator and my low voltage CMOS amplifier are both wellsuited for very low voltage application, they may be readily combined asbuilding blocks for a monolithic wrist watch, as shown in FIG. 5. Here,the oscillator output is connected directly to the input junction 42 andthe oscillator 62 is operated by the same power source V The capacitors40 and 46 and 72 are de signed in such a way that capacitor 72 is theparasitic pn-junction capacitance of capacitors 40 and 46.

In another alternative oscillator-amplifier arrangement according to thepresent invention, blocks shown in FIG. 5 using the Pierce typeoscillator amplifier may be replaced with another low voltage CMOSamplifier block 76 which serves as an oscillator, as shown in FIG. 6.This arrangement eliminates the need for both of the external resistorsR and R of the Pierce oscillator which are difficult to implementefficiently on an MOS device.

In order to achieve a high degree of frequency stability in thisarrangement, a lag network comprised of a resistor 78 and a capacitor 80may be used. The resistor 78 is connected between the output of theoscillating block 76 and the input to the amplifier block 10a and isalso connected by a feedback lead 82 through a crystal oscillator 84 tothe input of the oscillator block. The capacitor 80 is connected betweenthe resistor 78 and the input junction to the amplifier and ground.Since the resistivity of 78 is of the order of kilo ohms, it can beeasily integrated in monolithic form together with the other components.The crystal oscillator 84 provides an oscillating feedback signal tomaintain the de sired operating frequency of the circuit.

From the foregoing it should be apparent that the present invention notonly solves the biasing problem for a CMOS amplifier but also providesan amplifier which is operable under extremely low power requirements.This feature, coupled with its inherent simplicity of implementation andfunctional versatility makes it uniquely applicable to microelectronicdevices such as timing devices or watches,

To those skilled in the art to which this invention relates, manychanges in construction and widely differing embodiments andapplications of the invention will suggest themselves without departingfrom the spirit and scope of the invention. The disclosures and thedescription herein are purely illustrative and are not intended to be inany sense limiting.

I claim:

1. An amplifier comprising:

a pair of amplifying transistors connected to a common output junction,including a first transistor connected to a voltage supply line and asecond transistor connected to a ground-line;

a first lead extending from an input junction to the gate of said firstamplifying transistor and a second lead extending from said inputjunction to the gate of said second amplifying transistor, each of saidleads being connected through a capacitor means for preventing the flowof direct current; and

a pair of divider networks connected to said voltage supply line andsaid ground-line, each said network comprising a pair of biasingtransistors connected in series and with a junction between themconnected to at least one of said leads for the gates of said amplifyingtransistors.

2. The amplifier as described in claim 1 wherein one said networkcomprises a first biasing transistor connected between said supply lineand said first lead and a second biasing transistor connected betweensaid first lead and said ground line whose gate is connected to saidsupply line.

3. The amplifier as described in claim 1 wherein one said networkcomprises a first biasing transistor connected between said supply lineand said second lead and a second biasing transistor connected betweensaid second lead and said ground line whose gate is connected to saidsecond lead.

4. The amplifier as described in claim 1 wherein said first amplifyingtransistor is formed as a P-Channel element of an integrated circuitsemi-conductor device and said second amplifying transistor is anN-Channel element of the same device.

5. The amplifier as described in claim 4 wherein one transistor of eachsaid divider network is a P-Channel element of said integrated circuitdevice and the other transistor of each said divider network is anN-Channel element.

* I i t

1. An amplifier comprising: a pair of amplifying transistors connectedto a common output junction, including a first transistor connected to avoltage supply line and a second transistor connected to a ground-line;a first lead extending from an input junction to the gate of said firstamplifying transistor and a second lead extending from said inputjunction to the gate of said second amplifying transistor, each of saidleads being connected through a capacitor means for preventing the flowof direct current; and a pair of divider networks connected to saidvoltage supply line and said ground-line, each said network comprising apair of biasing transistors connected in series and with a junctionbetween them connected to at least one of said leads for the gates ofsaid amplifying transistors.
 1. An amplifier comprising: a pair ofamplifying transistors connected to a common output junction, includinga first transistor connected to a voltage supply line and a secondtransistor connected to a ground-line; a first lead extending from aninput junction to the gate of said first amplifying transistor and asecond lead extending from said input junction to the gate of saidsecond amplifying transistor, each of said leads being connected througha capacitor means for preventing the flow of direct current; and a pairof divider networks connected to said voltage supply line and saidground-line, each said network comprising a pair of biasing transistorsconnected in series and with a junction between them connected to atleast one of said leads for the gates of said amplifying transistors. 2.The amplifier as described in claim 1 wherein one said network comprisesa first biasing transistor connected between said supply line and saidfirst lead and a second biasing transistor connected between said firstlead and said ground line whose gate is connected to said supply line.3. The amplifier as described in claim 1 wherein one said networkcomprises a first biasing transistor connected between said supply lineand said second lead and a second biasing transistor connected betweensaid second lead and said ground line whose gate is connected to saidsecond lead.
 4. The amplifier as described in claim 1 wherein said firstamplifying transistor is formed as a P-Channel element of an integratedcircuit semi-conductor device and said second amplifying transistor isan N-Channel element of the same device.